In many current electronic devices, a discrete portion of main memory may be allocated to each of the programs running on the device. FIG. 1 shows one implementation of an exemplary prior art shared memory space 100. In FIG. 1 memory space 100 comprises a plurality of memory buffers (e.g., buffer 0-buffer 20) which are grouped to form 2 first-in first-out (FIFO) data queues, FIFO 0 and FIFO 1 are adjacent to and separated by a static boundary 1 (e.g., 130) which is indexed at a value of 10. Also shown in FIG. 1 is a static boundary 2 (e.g., 131) which separates FIFO 1 from the next adjoining FIFO and which is indexed at a value of 20. Also shown in FIG. 1 are a read pointer 0 (RP0) 111 which indicates that the next buffer in FIFO 0 into which data will be accessed, and a write pointer 0 (WP0) 112 which indicates the next buffer in FIFO 0 from which data will be stored. Similarly, FIFO comprises a RP1 121 and WP 122 which perform the same function for FIFO 1.
The operation of FIFO queues, also referred to as “circular buffers,” is well known in the art. When the write pointer for a FIFO queue has incremented to the highest value for the queue (e.g., 9 for FIFO 0), it returns to the lowest index value for the subsequent write operation. As shown in FIG. 1, WP0 (112) has incremented to 9 and then returned to 0 and 1 for subsequent write operations, thus indicating that buffer 1 will be the next data buffer to which data will be written. However, RP0 is indexed at 8 indicating that the data in buffers 8, 9, and 0 have not been read from and still contain current data. This phenomenon is referred to as “wrapping” as the data has been wrapped from the highest data buffer in the queue back around the lowest.
In FIFO 1, both RP1 (121) and WP1 (122) point to the same data buffer, data buffer 13. This can mean that FIFO 1 is either empty or full, depending upon which operation was last performed in FIFO 1. For example, if the last operation performed in FIFO 1 was a read operation, it would indicate that all of the current data stored in FIFO 1 was read before additional data was stored. If the last operation performed in FIFO 1 was a write operation, it would indicated that WP1 (122) has wrapped around as shown in FIG. 1. Typically, a subsequent write to FIFO 1 would be denied as it would over-write the data in buffer 13 that has not yet been accessed.
If an application is denied a write operation, it can adversely affect the performance of the currently running application when the FIFO acts as a bottleneck. To minimize the danger of this happening, FIFO queues are typically allotted an amount of space that would prevent a “worst case scenario” to avoid the bottleneck situation. However, oversizing the FIFO queues in this manner wastes memory space which might be more productively allocated to the currently running application. Additionally, as more functionality is built into devices and chip designers strive to ensure that no client is denied access to data, the number of FIFO queues on the chip is proliferating, thus consuming even more memory space and power.